JoyenBenitto

A Pragmatic Left-Shift Methodology—Tools & Techniques for Exploring and Building Domain-Specific SoCs

soc-designdsaleft-shifthardware-designverificationdomain-specific-architecture

May 13, 2025

Resources

IP-XACT-https://en.wikipedia.org/wiki/IP-XACT
SystemRDL-https://www.accellera.org/downloads/standards/systemrdl
SystemC-https://en.wikipedia.org/wiki/SystemC
TLM-2.0-https://en.wikipedia.org/wiki/SystemC#TLM_2.0
QEMU-https://en.wikipedia.org/wiki/QEMU
Bluespec SystemVerilog-https://github.com/B-Lang-org/bsc
Chisel-https://www.chisel-lang.org/
SpinalHDL-https://github.com/SpinalHDL/SpinalHDL
PyMTL3-https://github.com/pymtl/pymtl3
Clash-https://clash-lang.org/
rocket-chip-https://github.com/chipsalliance/rocket-chip
BOOM-https://github.com/riscv-boom/riscv-boom
VexRiscv-https://github.com/SpinalHDL/VexRiscv
Verilator-https://www.veripool.org/verilator/
GHDL-https://github.com/ghdl/ghdl
Icarus Verilog-https://github.com/steveicarus/iverilog
cocotb-https://www.cocotb.org/
SymbiYosys-https://github.com/YosysHQ/sby
Yosys-SAT-https://github.com/YosysHQ/yosys
FuseSoC-https://github.com/olofk/fusesoc
Edalize-https://github.com/olofk/edalize
Verible-https://github.com/chipsalliance/verible
reggen-https://github.com/lowRISC/opentitan/tree/master/util/reggen
SystemRDL-Compiler-https://github.com/SystemRDL/systemrdl-compiler
Cerberus-https://github.com/pyeve/cerberus
PySystemC-https://github.com/accellera-official/PySysC
OpenDSE-https://sdarg.github.io/opendse/
nevergrad-https://github.com/facebookresearch/nevergrad
pyswarms-https://github.com/ljvmiranda921/pyswarms
OpenROAD-https://github.com/The-OpenROAD-Project/OpenROAD
Genetic Algorithms-https://en.wikipedia.org/wiki/Genetic_algorithm
Simulated Annealing-https://en.wikipedia.org/wiki/Simulated_annealing
Particle Swarm Optimization-https://en.wikipedia.org/wiki/Particle_swarm_optimization
Network-on-Chip-https://en.wikipedia.org/wiki/Network_on_a_chip
Domain-Specific Architecture-https://en.wikipedia.org/wiki/Domain-specific_architecture

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