About
SoC Design Engineer at InCore Semiconductors. B.Tech ECE, PES University.
I build systems that communicate at the speed of silicon and reason about computation as code.
Work
SoC Design Engineer, InCore Semiconductors, IIT Madras Research Park (Jun 2024 – present)
Working on RISC-V SoC generation, platform tooling, and design automation. Key projects:
- DDSL (Device Drivers Specification Language), a DSL for generating device drivers from hardware specs
- Device Manager, scalable IP management framework; handles Verilog-to-BSV wrapper generation, test infrastructure, and third-party IP integration
- Pinmux Generator, real-time pin reconfiguration for packaging optimization
- SoC Generator, RISC-V SoC generator platform; FPGA emulation, Zephyr/baremetal software collateral, register smoke testing
Previously intern at InCore (Jun 2023 – May 2024), where I contributed to Azurite, a configurable RISC-V heterogeneous core generator.
Research Contributor, Centre for Heterogeneous and Intelligent Processing Systems, Bangalore (Oct–Dec 2023)
Contributed to PARISCV, a RISC-V application profiler for custom ISA optimization. Published at OSCAR’24.
Education
B.Tech, Electronics and Communication Engineering, PES University (Jun 2020 – Jun 2024)
Research focus: EDA, computer architecture, hardware-software co-design.
Teaching Assistant, RISC-V Architecture, PES University, Dept. of ECE (Oct–Dec 2023)
Community
Co-founder, Hyperthrd Computer Architecture Community (Oct 2023 – present)
Student-driven research community on computer architecture, technical discussions, reading groups, and workshops on RISC-V and hardware design.
Skills
| Domain | Tools |
|---|---|
| HDLs | SystemVerilog, Verilog, Bluespec SystemVerilog |
| Programming | Python, C, C++, Rust, Haskell |
| Tools | Git, Linux, Docker, CI/CD |
| Interests | Compilers, PL theory, formal methods, parallel computing |