Research
Research interests, projects, and publications.
My research interests sit at the convergence of computer architecture, design automation, and programming language theory. The central question: can we express what a system should do in a way that lets compilers handle how it gets built in silicon?
Interests
Hardware-software co-design. Partitioning computation between hardware and software at the right abstraction boundary, not as an afterthought, but as a design primitive.
Domain-specific languages for hardware. Type-safe, declarative languages that let engineers reason about topology, routing, and timing at specification time rather than discovering failures in RTL.
Architectural synthesis. Scheduling models, data-path generation, and the formal structures that connect algorithm descriptions to circuit implementations.
Types and PL theory applied to hardware. Typed systems restrict the design space in productive ways. Bluespec and Haskell show what this looks like in practice. What does a synthesis-friendly type theory look like?
Projects
Hermes,
warp-speed accelerator generator
A DSL for describing what an accelerator computes; the toolchain handles
partitioning, scheduling, and synthesis. Personal project, actively
developed.
DDSL, Device Drivers Specification Language
A transpiler from custom grammar to C for generating device drivers for
RISC-V SoCs. Built at InCore Semiconductors.
Device Manager
Scalable IP management framework for RISC-V SoC integration. Handles BSV
wrapper generation, test infrastructure, and documentation.
Pinmux Generator
Real-time pin reconfiguration tool. Takes packaging constraints as input
and produces optimized pinmux configurations.
PARISCV, RISC-V application profiler
Profiles application behavior to suggest custom ISA extensions.
Developed at CHIPS Bangalore.
Publications
“Hardware-Software Co-Design Methodologies for RISC-V Custom
ISA”
OSCAR’24, with the PARISCV team at Centre for Heterogeneous and
Intelligent Processing Systems, Bangalore.
“Enhancing Micro-Strip Patch Antenna Design for HFSS Using
AntGen”
IEEE MAPCON’23, Python package for antenna geometry generation.
Talks
| Talk | Venue | Date |
|---|---|---|
| SoC design and automation methodologies | Hyperthrd Community | Dec 2023 |
| Understanding RISC-V microarchitecture | PES University | Nov 2023 |
| Compilers, linkers, loaders with RISC-V GCC | Hackerspace | Oct 2023 |
| CUDA and data-level parallelism | PES University | Sep 2023 |
| NVIDIA Fermi GPU architecture | PES University | Aug 2023 |
| Data-level parallelism and SIMD | Advanced CA course | Jul 2023 |