comp-arch

• Designing a topology DSL for NoC synthesis 2026-03-14
  A declarative language for network-on-chip topology that compiles to RTL.
• Abstract Models
  Notes on abstract models and their role in high-level synthesis
• Architectural Synthesis
  Notes on architectural synthesis techniques and methodologies in HLS
• Butterfly on-chip network
  Notes on Butterfly networks
• On-chip Network Topology
  Notes on noc topologies